Ms. Ancy Joy

Assistant Professor

Employee Code / ID No.
Qualifications M.Tech in VLSI and Embedded Systems, Pursuing PhD
Orcid ID
Industry / R & D Experience Nil
Email ID [email protected]
Alternate E-mail ID
Mobile No (Optional) / Intercom Extension No.
Areas of Interest / Current Research VLSI, Embedded Systems, Low power VLSI, Memory Design
Research, Consultancy, Publication
  • Ancy Joy, Jinsa Kuruvilla, “A Stable Low Power Dissipating 9T SRAM For Implementation of 4×4 Memory Array with High Frequency Analysis”, Wireless Personal Communication (2022), Springer [SCIE Indexed].
  • Megha Aby Thomas, Anjana K, Ancy Joy, & Kuruvilla, J. “Forced-Sleep SVR SRAM for High Frequency Applications” , International Conference on Power Electronics and Renewable Energy Applications (PEREA), 2020, pp 1-5.
  • Sruthi James ,Ancy Joy &  Dr.K.T Mathew High Efficiency, “Flash ADC Using High Speed Low Power Double Tail Comparator” , IJAREEIE, Vol. 4, Issue 11, November 2015, pp-9287-9292.
  • Ancy Joy & Sani John, “ Dynamic Shift to Reduce Test Data Volume in Sequential Circuit Testing”, IJAREEIE, Vol. 5, Issue 1, January 2016, pp-61-65.
  • Ancy Joy,Sani John & Sruthi James “FPGA Implementation of Functional Broadside Test Using Fixed Hardware Structure”, IJAREEI E, Vol. 4, Issue 11, November 2015, pp-9235-9239.
  • Ancy Joy & Sani John, “Dynamic Shift scan with Area efficiency”, IJAREEIE, Vol. 5, Issue 3, March 2016, pp-1233-1237.
Ph.D Research Guidance ( Research Scholar, E-mail ID, Research Topic/ Tentative Thesis Tittle) Nil
Academic / Professional Outreach Activities Gate coaching, Co-odinator of IEEE Woman in Engineering
Membership in Professional bodies/ organizations Member IEEE, IEEE Wie
Community Outreach Activities
Awards / Distinctions / Rank / Other Achievements if any UGC-NET 2016  qualified